Suitable for use in a one- or two-semester course for computer and electrical engineering majors. VHDL for Engineers teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
1. Digital Design Using VHDL and PLDs
2. Entities, Architectures, and Coding Styles
3. Signals and Data Types
4. Dataflow Style Combinatinal Design
5. Behavioral Style Combinational Design
6. Event-Driven Simulation
7. Testbenches for Combinational Designs
8. Latches and Flip-flops
9. Multibit Latches, Registers, Counters, and Memory
10. Finite State Machines
etc.